Silicon Oxynitride Based Encapsulation Layer for Magnetic Tunnel Junctions

ABSTRACT

A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.

PRIORITY DATA

The present application is a divisional application of U.S. patent application Ser. No. 15/619,825, filed Jun. 12, 2017, herein incorporated by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to magnetic tunnel junctions (MTJs) in magnetic random access memory (MRAM), spin-torque MRAM, and other spintronic devices, and in particular to protecting MTJ sidewalls during processing steps including the deposition of an encapsulation layer that separates adjacent MTJs, and during high temperature annealing around 400° C. that is common in Complementary Metal Oxide Semiconductor (CMOS) fabrication.

BACKGROUND

A MTJ is a key component in MRAM, spin-torque MRAM, and other spintronic devices and comprises a stack with a tunnel barrier layer such as a metal oxide formed between two magnetic layers that provides a tunneling magnetoresistance (TMR) effect. One of the magnetic layers is a free layer and serves as a sensing layer by switching the direction of its magnetic moment in response to external fields while the second magnetic layer has a magnetic moment that is fixed and functions as a reference layer. The electrical resistance through the tunnel barrier layer (insulator layer) varies with the relative orientation of the free layer moment compared with the reference layer moment and thereby provides an electrical signal that is representative of a magnetic state in the free layer. In a MRAM, the MTJ is formed between a top conductor and bottom conductor. When a current is passed through the MTJ, a lower resistance (Rp) is detected when the magnetization directions of the free and reference layers are in a parallel state and a higher resistance is noted when they are in an anti-parallel state. The magnetoresistive ratio (DRR) may be expressed as dR/R_(p) where dR is the difference in resistance between the two magnetic states. Since MTJ elements are often integrated in CMOS devices, the MTJ must be able to withstand annealing temperatures around 400° C. for about 30 minutes that are commonly applied to improve the quality of the CMOS units for semiconductor purposes.

Spin-torque (STT)-MRAM based technologies are desirable for nonvolatile memory applications. However, realizing low critical dimensions below 100 nm that match those found in Dynamic Random Access Memory (DRAM) is a challenge.

MTJs are highly susceptible to sidewall damage, both chemical and physical, induced by etching and deposition processes, and exacerbated by the CMOS process requirement of annealing at 400° C.

During fabrication of STT-MRAM devices, a MTJ nanopillar is typically defined by forming a pattern in an uppermost hard mask layer in the MTJ stack of layers, and then employing a physical etch (ion beam etch or IBE) or a chemical etch such as a reactive ion etch (RIE) with methanol to transfer the pattern through the MTJ stack thereby forming a plurality of MTJ nanopillars each with a critical dimension that is less than 100 nm for advanced devices. Subsequently, an encapsulation layer is deposited to electrically isolate MTJs from each other. The process flow of MTJ etching and encapsulation is a critical part of the CMOS integration flow and strongly influences the tunneling magnetoresistance ratio, especially for sub-100 nm device sizes.

The material and process selected to form the encapsulation layer around MTJ nanopillars must satisfy several criteria. In order to electrically isolate adjacent MTJs, the encapsulation layer must be a good dielectric material. Secondly, a tunnel barrier layer such as MgO is usually very hygroscopic which means the encapsulation layer should be an efficient moisture barrier. With regard to these two requirements, silicon based dielectric layers such as silicon oxide and silicon nitride have proven to be suitable encapsulation layer materials.

As spacial density of MRAM devices increases leading to a higher number of devices per unit area, the physical gap between adjacent MTJ nanopillars decreases. Therefore, a preferred encapsulation layer deposition method is one that provides excellent gap filling capability. In other words, highly conformal coatings provided by chemical vapor deposition (CVD) or atomic layer deposition (ALD) should be more suitable for such applications compared with physical vapor deposition (PVD) where shadowing effects are more severe.

In view of MRAM integration into CMOS technology, the encapsulation material needs to withstand exposure to 400° C. for two hours or more, and also protect the MTJ sidewall at these conditions.

There is a need to provide an encapsulation layer and process that meets all of the aforementioned requirements, especially for state of the art memory devices with a critical dimension of less than 100 nm.

SUMMARY

One objective of the present disclosure is to substantially improve the magnetoresistive ratio of a MTJ nanopillar by minimizing the exposure of MTJ sidewalls to reactive species during formation of an encapsulation layer that electrically isolates MTJ nanopillars from one another.

A second objective of the present disclosure is to provide a material that enables the encapsulation method of the first objective, and also satisfies the thermal stability, dielectric, moisture resistance, and gap filling requirements for MRAM devices that are integrated into CMOS technology.

According to one embodiment of the present disclosure, these objectives are achieved by providing a plurality of MTJ nanopillars on a substrate that may be a bottom electrode layer in a MRAM or STT-MRAM, for example. Adjacent MTJ nanopillars are separated from each other by gaps where each gap exposes a portion of the substrate top surface. Preferably, a first encapsulation layer that is silicon oxynitride (SiOxNy), where x and y are both >0, is conformally deposited on the substrate and on the plurality of MTJ nanopillars and their sidewalls to partially fill the gaps by a plasma enhanced CVD (PECVD) method. In other embodiments, an atomic layer deposition (ALD) technique, a CVD process method, or PVD process is employed to deposit the silicon oxynitride layer hereinafter expressed as SiON. Thereafter, a second encapsulation layer that is Al₂O₃, SiO₂, or other oxides, nitrides, oxynitrides, or carbonitrides used in the art to electrically isolate adjacent MTJ nanopillars is deposited on the first encapsulation layer and completely fills the gaps. Next, a chemical mechanical polish (CMP) process is performed to remove an upper portion of the first and second encapsulation layers such that top surfaces thereof are coplanar with top surfaces of the MTJ nanopillars.

According to one embodiment, a critical feature is that the SiON layer is deposited with a PECVD process comprising a first step wherein there is a nitrous oxide (N₂O):silane flow rate ratio that is greater than 1:1, and less than 15:1. As a result, substantially all of the N₂O is consumed during formation the SiON layer and thereby minimizes attack of reactive oxygen containing species on the MTJ sidewalls. Moreover, keeping the flow rate ratio above 1:1 minimizes the volume of unreacted silane in the SiON layer. An inert carrier gas including one or more of Ar, Kr, He, and Ne may also be fed into the PECVD deposition chamber during SiON deposition to enable a gas flow that sustains a plasma. The PECVD process typically comprises a temperature from 220° C. to 400° C., and a RF power from 100 to 1500 Watts to generate a plasma of reactive species that combine to form the SiON layer on the MTJ nanopillars.

In another embodiment, the PECVD process that forms the first encapsulation layer comprises two steps wherein a first SiON layer is deposited on the MTJ nanopillars with a PECVD step comprising a nitrous oxide (N₂O):silane flow rate ratio of between 1:1 and 5:1, and then a second SiON layer is formed on the first SiON layer with a second PECVD step having a N₂O:silane flow rate ratio greater than the first N₂O:silane flow rate ratio, and preferably greater than 5:1 and less than 15:1. The second step is performed immediately after the first step is completed and both steps comprise generating a plasma in a reaction chamber with a temperature from 220° C. to 400° C., a radio frequency (RF) power, and a noble gas flow. As a result, exposure of MTJ sidewalls to reactive oxygen and nitrogen species during formation of the first SiON layer is minimized, and the concentration of unreacted silane in the first encapsulation layer is minimized during deposition of the second SiON layer.

After a desired first encapsulation layer thickness is formed, the next step in the PECVD process is initiated wherein a N₂O plasma treatment is performed. The N₂O plasma treatment may be performed in the same process chamber where the first encapsulation layer is deposited. The present disclosure anticipates that after a first period of time has elapsed to complete the deposition of the first encapsulation layer, the first reactant flow rate is immediately stopped while the N₂O flow rate and resulting plasma treatment continues for a second period of time. The N₂O plasma treatment is advantageously used to ensure that residual silane in the first encapsulation layer is consumed. Furthermore, the first encapsulation layer is believed to become more dense during the second step thereby preventing reactive species formed in a subsequent deposition of the second encapsulation layer from penetrating the first encapsulation layer and attacking MTJ sidewalls. Since the first encapsulation layer only partially fills the gaps between adjacent MTJs, the second encapsulation layer is employed to completely fill the gaps.

After a CMP process planarizes the first and second encapsulation layers, a top electrode layer is formed such that a conductive line in the top electrode layer contacts a top surface of each MTJ nanopillar in a row or column in the memory array. The completed memory structure may be a MRAM, STT-MRAM, or a spintronic device such as a spin torque oscillator (STO). In a STO device, the substrate may be a main pole layer that serves as a bottom electrode, and the top electrode may be a trailing shield, for example.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view that depicts a memory structure having first and second encapsulation layers formed on MTJ sidewalls, and deposited by a PECVD process according to an embodiment of the present disclosure.

FIG. 2 is a cross-sectional view that illustrates a second embodiment of the present disclosure wherein the first encapsulation layer in FIG. 1 is modified to include two SiON sub-layers.

FIG. 3 is a cross-sectional view that shows a step of forming a MTJ nanopillar structure by using a masking layer during an etching process according to an embodiment of the present disclosure.

FIG. 4 is a cross-sectional view depicting the partially formed memory structure in FIG. 3 after a PECVD process is used to deposit the first encapsulation layer according to an embodiment of the present disclosure.

FIG. 5 is a cross-sectional view depicting the partially formed memory structure in FIG. 4 after a second encapsulation layer is deposited to cover a plurality of MTJ nanopillars according to an embodiment of the present disclosure.

FIG. 6 is a cross-sectional view of the intermediate structure in FIG. 5 after a chemical mechanical polish (CMP) process is performed to form a planar top surface on the second encapsulation layer according to an embodiment of the present disclosure.

FIG. 7 is a top-down view of the memory structure in FIG. 1 that shows an array of MTJ nanopillars formed in rows and columns according an embodiment of the present disclosure.

FIG. 8 is a plot of magnetoresistive ratio (DRR) as a function of Rp that is related to MTJ size, and shows improved performance when a first encapsulation layer is formed according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

The present disclosure relates to an improved encapsulation layer comprised of SiON that adjoins MTJ nanopillars, and in particular, to a process for depositing the same that substantially minimizes damage to MTJ sidewalls and thereby yields a higher magnetoresistive ratio, especially for critical dimensions of 100 nm or less.

The MTJ nanopillars may be formed in a variety of memory devices including but not limited to MRAM, spin-torque MRAM, and other spintronic devices such as a spin torque oscillator (STO). In the drawings, a thickness of a layer is in the z-axis direction, and the plane of each layer is formed in the x-axis and y-axis directions.

As indicated earlier, encapsulation materials such as silicon oxide and silicon nitride that are deposited by excellent gap filling methods such as CVD, or with a less thermally stringent PECVD process, satisfy several requirements including serving as an efficient moisture barrier, providing excellent dielectric properties, and having thermal stability to 400° C. However, we observe that precursor materials used for depositing silicon oxide and silicon nitride are highly reactive and readily attack MTJ sidewalls. For example, silicon nitride deposition uses silane and ammonia, and we found that exposure of MTJ sidewalls to reactive ammonia species significantly reduces the magnetoresistive ratio (DRR) of the MTJ nanopillars. Similarly, silicon oxide deposition employs silane and nitrous oxide (N₂O) where a large volume of N₂O relative to that of silane is necessary. As a result, MTJ sidewalls are easily oxidized by an abundance of reactive oxygen containing species.

Although silicon oxynitride is also deposited with silane and N₂O precursors, we have discovered that by limiting the flow rate of N₂O relative to that of silane, DRR is substantially improved over prior art methods, especially for MTJ sizes less than 100 nm. Moreover, a N₂O plasma treatment may follow the SiON deposition to ensure that essentially no unreacted silane remains in the film. It is believed that with a N₂O/silane flow rate ratio below 15:1, a considerable amount of unreacted silane may remain in the SiON layer, and during subsequent processing, residual silane reacts with a tunnel barrier layer such as MgO thereby lowering DRR.

Referring to FIG. 1, a first embodiment of the present disclosure is shown wherein a memory device comprises a plurality of MTJ nanopillars hereafter called MTJs including MTJ 11 a and MTJ 11 b that have sidewalls 11 s 1 and 11 s 2, respectively, and adjoin a first encapsulation layer 12. MTJ 11 a is formed between a bottom electrode 10 a and a top electrode 14 a while MTJ 11 b contacts bottom electrode 10 a and top electrode 14 b. Second encapsulation layer 13 is formed on the first encapsulation layer and fills a majority of the space (gap) between adjacent MTJ nanopillars. The stack of first and second layers 12, 13 is considered a bilayer configuration for the encapsulation layer that is also referred to as a passivation layer. The bottom electrode is a line that extends along the x-axis, and the top electrodes are lines that extend in the y-axis direction in a MRAM or STT-MRAM embodiment. Bottom and top electrodes are typically comprised of one or more metals or alloys to ensure excellent electrical conductivity and resistance to oxidation. There is an insulation layer 15 formed on a substantial portion of second encapsulation layer top surface 13 t. Within the insulation layer is a top electrode layer comprised of top electrodes including 14 a, 14 b. Note that each of the top electrodes may have a width w1 that is greater than a width of top surfaces 11 t 1, and 11 t 2. In other words, an outer portion of the top electrodes may overlay on the first encapsulation layer and on a portion of the second encapsulation layer.

It should be understood that typically millions of MTJs are aligned in rows and columns in a memory array on a substrate, and each MTJ is formed between a bottom electrode and a top electrode. However, the number of MTJs shown in FIG. 1 is limited to two in order to simplify the drawing. The MTJs may have a variety of configurations but each MTJ has at least a tunnel barrier layer formed between a reference layer (RL) and free layer (FL) in a RL/tunnel barrier/FL or FL/tunnel barrier/RL stack on a substrate (not shown) that is a seed layer, for example.

First encapsulation layer 12 contacts not only MTJ sidewalls 11 s 1 and 11 s 2, and other MTJ sidewalls that are not depicted, but also adjoins portions of top surfaces of bottom electrodes such as top surface 10 t of bottom electrode 10 a that are not covered by MTJs. Preferably, the first encapsulation layer has a uniform (conformal) thickness from 10 to 200 Angstroms. According to one aspect, the first encapsulation layer is SiO_(X)N_(Y) where each of x and y is >0, and which is deposited by a PECVD process or the like that minimizes exposure of MTJ sidewalls to reactive oxygen species, and significantly reduces the amount of unreacted silane in the deposited SiON layer.

In a preferred embodiment, first encapsulation layer 12 is deposited by a PECVD method that is performed in a reaction chamber at a temperature from 220° C. to 400° C. The PECVD process may be “in-situ” in that it is performed in the same mainframe that was used to etch MTJ sidewalls 11 s 1, 11 s 2. For example, the mainframe may have a first reaction chamber for the MTJ etch process, and an adjacent second reaction chamber for PECVD that is linked to the first reaction chamber by a track system maintained under an inert atmosphere to exclude oxygen. The track system is used to transport wafers from one chamber to another chamber in the mainframe. Alternatively, the PECVD process is ex-situ wherein the first encapsulation layer deposition occurs in a different tool outside of a mainframe in which the MTJ etch process occurred. Although a CVD process could be employed for forming the first encapsulation layer, CVD usually comprises a temperature considerably higher than 400° C. that could damage one or more layers in the MTJ nanopillars. Alternatively, PVD or ALD could be selected to deposit the first encapsulation layer. However, the former typically does not provide the necessary gap filling capability while ALD deposition is slower than PECVD and may undesirably lengthen throughput time.

In one preferred embodiment, the PECVD process is performed with a mixture of silane and nitrous oxide (N₂O) as reactants. Furthermore, a critical feature is providing a N₂O/silane flow rate ratio of at least 1:1, and preferably greater than 5:1 but less than 15:1. In some embodiments, the N₂O flow rate is maintained in the range of 110 to 500 standard cubic centimeters per minute (sccm) to provide a SiON (first encapsulation layer) thickness of 10 to 200 Angstroms during a period of 3 to 60 seconds. It should be understood that with a N₂O:silane flow rate ratio of 15:1 or greater, a considerable amount of SiO₂ is formed in the deposited film, and the concentration of excess reactive oxygen species during deposition is sufficiently high to pose a significant risk of attack on MTJ sidewalls. In the prescribed flow rate ratio range, essentially all of the nitrous oxide is consumed during formation of SiON, which leaves a relatively small volume of reactive oxygen species, if any, to oxidize MTJ sidewalls. Furthermore, the amount of unreacted silane residing in the deposited SiON layer is minimized in the prescribed flow rate ratio range to avoid a threat of a subsequent reaction of residual silane that could reduce the oxidation state in an adjoining tunnel barrier layer in the MTJ nanopillars. Accordingly, DRR for the encapsulated MTJs is improved compared with conventional deposition processes that employ a silane:N₂O flow rate ratio outside of the prescribed range disclosed herein.

In another embodiment depicted in FIG. 2, the first encapsulation layer 12 comprises two SiON sub-layers each formed by different PECVD conditions. A first PECVD step is employed to deposit a first SiON sub-layer 12-1 by using a first N₂O:silane flow rate ratio between 1:1 and 5:1. Immediately after the first SiON sub-layer is laid down, a second PECVD step in the same chamber is performed to deposit a second SiON sub-layer 12-2 with a second N₂O:silane flow rate ratio that is greater than the first N₂O:silane flow rate ratio, and preferably greater than a 5:1 flow rate ratio, but where the N₂O flow rate is less than 15 times the silane flow rate. Both PECVD steps generate a plasma with a temperature from 220° C. to 400° C., a radio frequency (RF) power, and a noble gas flow in addition to the N₂O and silane flows. The first and second sub-layers have a combined thickness of 10 to 200 Angstroms. The first sub-layer has a Si_(x1)O_(Y1)N_(z1) composition and the second sub-layer has a Si_(x2)O_(Y2)N_(z2) composition where _(x1) and _(x2) are the Si content in the first and second sub-layers, respectively, and _(x1) is unequal to _(x2). Preferably, _(x1) is greater than _(x2) as a result of a higher silane content in the gas mixture used during deposition of the first SiON sub-layer.

After a desired thickness of the first encapsulation layer 12 is achieved, the PECVD process immediately continues to a second step in the same reaction chamber. In particular, the silane flow rate is terminated while all other conditions including temperature, RF power, and N₂O flow rate are maintained from the first step for an additional period of time of 3 to 20 seconds. In some embodiments, the RF power during the N₂O plasma treatment may be reduced to a minimum of 25 Watts from a minimum of 100 Watts in the first step. Although not bound by theory, it is believed that during the second step, N₂O plasma is advantageously used to react with residual silane in the first encapsulation layer to prevent a subsequent reaction of residual silane with the tunnel barrier layer. Also, the first encapsulation layer is believed to become denser as a result of the N₂O plasma treatment thereby generating a more impervious barrier to reactive species during the subsequent step of depositing the second encapsulation layer 13 on the first encapsulation layer. Accordingly, a first encapsulation layer with higher density offers improved protection against attack by reactive oxygen species and the like on MTJ sidewalls.

In all of the aforementioned embodiments, the PECVD process used to deposit the first encapsulation layer 12 comprises a RF power of 100 to 1500 Watts and a chamber pressure from 4 to 6 torr. The present disclosure also anticipates the addition of a noble carrier gas such as Ar, Kr, Ne, or He to transport the silane and N₂O precursors into the reaction chamber. The advantage of including the noble carrier gas is to provide a sufficient flow of materials in order to maintain a plasma in the reaction chamber.

The second encapsulation layer 13 is typically a metal oxide, metal carbide, metal nitride, metal oxynitride, or metal carbonitride such as SiO_(v)N_(w), AIO_(v)N_(w), TiO_(v)N_(w), SiC_(v)N_(w), or MgO or any combination of the aforementioned materials where v+w>0. The second encapsulation layer has a thickness up to about 2000 Angstroms and is typically thicker than the first encapsulation layer. In some embodiments, the second encapsulation layer has a faster deposition rate than the first encapsulation layer and is relied upon to fill gaps between adjacent MTJs that remain after the first encapsulation layer is laid down. Usually, the second encapsulation layer fills a major portion of the gaps between adjacent MTJ nanopillars in view of having a greater thickness than the first encapsulation layer.

Referring to FIG. 3, a process of forming a plurality of MTJs in a memory array is depicted. A photoresist layer is formed on the MTJ stack of layers and is patterned by a well known photolithography technique to give a plurality of islands including photoresist islands 30 a, 30 b each having a width w. Subsequently, a conventional reactive ion etch (RIE), an ion beam etch (IBE) process, or a combination of a chemical etch (RIE) and physical etch (IBE) called RIBE is performed to remove regions of the MTJ stack of layers that are not protected by a photoresist island. Note that the photolithography process yields an array of photoresist islands laid out in rows and columns such that each island serves as an etch mask. Furthermore, the RIE, IBE, or RIBE process may include a plurality of steps and generates a MTJ sidewall below each etch mask. Thus, MTJ 11 a and MTJ 11 b are formed with sidewalls 11 s 1 and 11 s 2, respectively, below islands 30 a and 30 b, and there are gaps 50 on each side of the MTJs that expose portions of bottom electrode top surface 10 t. In the exemplary embodiment, the RIE, IBE, or RIBE process forms non-vertical sidewalls 11 s 1 and 11 s 2 such that a bottom of each MTJ at top surface 10t has a greater width than w. However, depending on the MTJ etch conditions, substantially vertical MTJ sidewalls may be produced.

Referring to FIG. 4, a conventional process is employed to remove photoresist islands 30 a, 30 b. Then, first encapsulation layer 12 is deposited on top surface 10 t and on the array of MTJs including top surfaces 11 t 1 and 11 t 2, and sidewalls 11 s 1 and 11 s 2 of MTJ 11 a and MTJ 11 b, respectively, according to a process that was previously described. In a preferred embodiment, the PECVD deposition process is substantially conformal such that a uniform thickness of first encapsulation layer is formed on the MTJ top surfaces and on MTJ sidewalls.

In FIG. 5, the partially formed memory structure in FIG. 4 is depicted after the second encapsulation layer 13 is deposited by a PECVD or CVD process on the first encapsulation layer 12. ALD or PVD methods may be selected for this step but are generally associated with a lengthy deposition time or poor gap filling capability, respectively. The top surface of the second encapsulation layer has topography in view of multiple maximum points 13 t 2 above the MTJs 11 a, 11 b, and a plurality of minimum points 13 t 1 about midway between the maximum points. Minimum points are a distance d>0 above plane 22-22 that includes top surfaces 11 tl, 11 t 2 of the MTJs. In other words, the first and second encapsulation layers completely fill gaps 50 between adjacent MTJs 11 a, 11 b.

Referring to FIG. 6, a well known chemical mechanical polish (CMP) process is performed to remove an upper portion of the encapsulation layer with the bilayer configuration such that the partially formed memory device has a top surface along plane 22-22 that includes first encapsulation layer top surface 12t, second encapsulation layer top surface 13 t, and top surfaces 11 t 1 and 11 t 2 of MTJ 11 a and MTJ 11 b, respectively. In some embodiments, the uppermost MTJ layer is a hard mask such as MnPt with a top surface that is 11 t 1 or 11 t 2. In other embodiments, the uppermost MTJ layer is a capping layer that is one or more of SiN, TiN, Ta, Ti, W, or Ru such as a Ru/Ta/Ru configuration, for example.

Returning to the first embodiment in FIG. 1 or the second embodiment in FIG. 2, a subsequent sequence of steps well known in the art is followed and includes photoresist patterning and etch processes that are used to form a top electrode layer with top electrodes 14 a, 14 b within insulation layer 15 wherein top electrode 14 a adjoins the top surface of MTJ 11 a, and top electrode 14 b contacts the top surface of MTJ 11 b. As mentioned previously, the top electrode layer typically comprises a plurality of top electrodes formed in an array of parallel lines, for example, but only two top electrodes are shown in the exemplary embodiment. The insulation layer may be silicon oxide or alumina, or other dielectric materials that are used in the art to electrically isolate adjacent conductive elements, and has a bottom surface at plane 22-22.

Referring to FIG. 7, a top-down view of the memory structure in FIG. 1 (or FIG. 2 is depicted. Plane 20-20 indicates the location where the cross-sectional views in FIG. 1 (or FIG. 2) is taken. In the exemplary embodiment where an additional two MTJs 11 c and 11 d are shown between a second bottom electrode 10 b and top electrodes 14 a, 14 b, respectively, the width w1 of the top electrodes is preferably greater than the width w of the MTJs 11 a-11 d. Also, a length b of the bottom electrodes 10 a, 10 b in the y-axis direction is typically greater than the length c of the MTJs. The MTJs have a substantially circular shape that is a circle or ellipse. In other embodiments, the MTJs may have a polygonal shape such as a square or rectangle.

Referring to FIG. 8, an experiment was conducted to demonstrate the improved performance achieved by depositing a SiON first encapsulation layer to protect adjoining MTJ nanopillars according to an embodiment of the present disclosure. A series of MTJ nanopillars was fabricated in a circular shape (w=c in FIG. 7) on wafers wherein the MTJ diameter w was varied from around 30 nm to 300 nm on each wafer. With a first set of wafers that serve as a reference sample, a first encapsulation layer with a 200 Angstrom thickness and made of silicon oxide was deposited by a conventional PECVD method using a silane flow rate of 260 sccm, a N₂O flow rate of 3900 sccm, and a RF power of 300 Watts to partially fill the gaps between adjacent MTJs. Thereafter, a second encapsulation layer made of silicon nitride with a 2000 Angstrom thickness was deposited to fill the gaps. Then, a CMP process was performed, and a top electrode layer was formed within an insulation layer to yield a memory structure similar to that shown in FIG. 1. The completed memory structure was annealed at 400° C. prior to DRR measurements.

A second set of wafers having the same series of MTJ sizes mentioned previously, and that also serves as a reference was processed with a flow sequence similar to the first set of wafers except that the first encapsulation layer was a 200 Angstrom thick silicon nitride layer deposited by a conventional PECVD method using a 220 sccm silane flow rate, a 75 sccm NH₃ flow rate, a 5000 sccm N₂ flow rate, and a RF power of 450 Watts to partially fill the gaps between adjacent MTJs.

Finally, with a third set of wafers and the same series of MTJ sizes, the process flow of the first and second set of wafers was followed except the first encapsulation layer was SiON, and deposited according to an embodiment of the present disclosure. In particular, the PECVD process employed a 110 sccm silane flow rate, a 210 sccm N₂O flow rate, a 3800 sccm He flow rate, a pressure of 5.5 torr, and a RF power of 120 Watts. Each of the PECVD processes that were used to deposit the first encapsulation layers in the three sets of wafers was performed at 400° C. With the third set of wafers, a N₂O plasma treatment was applied for 20 seconds at 400° C. with a 2000 sccm N₂O flow, 4.8 Torr pressure, and a RF power of 200 Watts immediately after the SiON first encapsulation layer was deposited. Thus, each of the three sets of wafers had a 2000 Angstroms thick second encapsulation layer made of silicon nitride formed on a 200 Angstroms thick first encapsulation layer. DRR measurements were obtained with an Accretech UF300A prober at 25° C.

Results in FIG. 8 show that the series of MTJs 40 on the first set of wafers with a silicon oxide encapsulation layer exhibited the lowest DRR values. The series of MTJs 41 on the second set of wafers with a silicon nitride encapsulation layer provided a large improvement over the first series. However, the series of MTJs 42 on the third set of wafers with a SiOxNy first encapsulation layer deposited according to a method of the present disclosure, yielded the highest DRR values, especially for MTJ sizes proximate to 100 nm and below that correspond to Rp values between 10³ and 10⁴ Ohms.

The SiON encapsulation layer that is deposited by the PECVD process disclosed herein is expected to satisfy all of the requirements for an encapsulation layer employed in state of the art memory structures. In addition to having excellent gap filling capability, a low dielectric constant, and serving as an efficient moisture barrier, the first encapsulation layer has essentially no residual silane and is deposited with a process that enables an improved capacity to protect MTJ sidewalls from reactive species during formation of the first and second encapsulation layers.

While this disclosure has been particularly shown and described with reference to, the preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of this disclosure. 

We claim:
 1. A method comprising: forming a first magnetic tunnel junction (MTJ) and a second MTJ over a bottom electrode; and forming a first encapsulation layer over sidewalls of the first MTJ and the second MTJ, the first encapsulation layer including: a first sub-layer physically contacting the sidewalls of the first MTJ and the second MTJ, the first sub-layer further physically contacting the bottom electrode, the first sub-layer having a Si_(X1)O_(Y1)N_(Z1) composition; and a second sub-layer disposed on the first sub-layer, the second sub-layer having a Si_(X2)O_(Y2)N_(Z2) composition, wherein x₁ and x₂ are a Si content in the first and second sub-layers, respectively, wherein x₁>x₂, and wherein z₁ and z₂ are a N content in the first sub-layer and the second sub-layer, respectively.
 2. The method of claim 1, wherein the second sub-layer interfaces with the first sub-layer.
 3. The method of claim 1, wherein the forming of the first encapsulation layer over sidewalls of the first MTJ and the second MTJ includes forming the first sub-layer directly on top surfaces of the first and second MTJs, the top surfaces of the first MTJ and the second MTJ facing away from the bottom electrode.
 4. The method of claim 3, further comprising: forming a second encapsulation layer over the first encapsulation layer including between the first MTJ and the second MTJ, the second encapsulation layer formed of a different material than the first encapsulation layer; removing a portion of the second encapsulation and the first encapsulation to thereby expose the top surfaces of the first and second MTJs; forming a top electrode on the exposed top surfaces of the first and second MTJs.
 5. The method of claim 4, wherein the second encapsulation layer includes a material selected from the group consisting of a metal oxide, metal carbide, metal nitride, metal oxynitride and metal carbonitride.
 6. The method of claim 1, wherein the first MTJ has a upper portion having a first width and a lower portion having a second width that is different from the first width.
 7. The method of claim 1, wherein the forming of the first encapsulation layer over sidewalls of the first MTJ and the second MTJ includes: depositing the first sub-layer by using a first N₂O:silane flow rate ratio between 1:1 and 5:1; and depositing the second sub-layer over the first layer by using a second N₂O:silane flow rate ratio that is greater than a 5:1 but less than 15:1.
 8. A method comprising: forming a magnetic tunnel junction (MTJ) over a bottom electrode, the MTJ including a first sidewall and an opposing second sidewall and a top surface extending from the first sidewall to the second sidewall; forming a first SiON encapsulation layer directly on the first sidewall, the second sidewall and the top surface of the MTJ, the first SiON encapsulation layer having a first silicon content; and forming a second SiON encapsulation layer directly on the first SiON encapsulation layer disposed on the first sidewall, the second sidewall and the top surface of the MTJ, the second SiON encapsulation layer having a second silicon content that is different than the first silicon content.
 9. The method of claim 8, wherein the second silicon content is less than the first silicon content.
 10. The method of claim 8, wherein the forming of the first SiON encapsulation layer includes using a first N₂O:silane flow rate ratio; and wherein the forming of the second SiON encapsulation layer includes using a second N₂O:silane flow rate ratio that is greater than the first N₂O:silane flow rate ratio.
 11. The method of claim 10, wherein the first N₂O:silane flow rate ratio is between 1:1 and 5:1, and wherein the second N₂O:silane flow rate ratio is greater than 5:1 but less than 15:1.
 12. The method of claim 8, wherein the forming of the MTJ over the bottom electrode includes patterning the MTJ using a process selected from the group consisting of a reactive ion etch process and an ion beam etch.
 13. The method of claim 8, wherein the MTJ is part of a MRAM, spin torque (STT) MRAM, or a spin torque oscillator (STO) structure.
 14. The method of claim 8, further comprising: removing a first portion of the second SiON encapsulation layer and a first portion the first SiON encapsulation layer to thereby expose the top surface of the MTJ; and forming a top electrode directly on the exposed top surface of the MTJ.
 15. The method of claim 14, further comprising forming another encapsulation layer over the second SiON encapsulation layer, the another encapsulation layer formed of a different material than the second SiON encapsulation layer, and wherein the removing of the first portion of the second SiON encapsulation layer and the first portion of the first SiON encapsulation layer to thereby expose the top surface of the MTJ further includes removing a first portion of the another encapsulation layer, and wherein a second portion of the second SiON encapsulation layer, a second portion of the first SiON encapsulation layer and a second portion of the another encapsulation layer are disposed on the MTJ after forming the top electrode directly on the exposed top surface of the MTJ.
 16. A method comprising: forming a magnetic tunnel junction (MTJ) pillar over a bottom electrode, the MTJ pillar including a first slanted sidewall and an opposing second slanted sidewall and a top surface extending from the first slanted sidewall to the second slanted sidewall, the MTJ pillar being wider at an interface with the bottom electrode than at a portion of the MTJ pillar positioned away from the interface; forming a first SiON encapsulation layer on the first slanted sidewall and the top surface of the MTJ, the first SiON encapsulation layer having a first silicon content; forming a second SiON encapsulation layer on the first SiON encapsulation layer disposed on the first sidewall and the top surface of the MTJ pillar, the second SiON encapsulation layer having a second silicon content that is different than the first silicon content; and removing the first SiON encapsulation layer and the second SiON encapsulation layer from over the top surface of the MTJ pillar thereby exposing the top surface of the MTJ pillar.
 17. The method of claim 16, further comprising forming a top electrode on the exposed top surface of the MTJ pillar.
 18. The method of claim 17, wherein the removing of the first SiON encapsulation layer and the second SiON encapsulation layer from over the top surface of the MTJ pillar include performing a planarization process.
 19. The method of claim 16, wherein forming the first SiON encapsulation layer on the first slanted sidewall and the top surface of the MTJ includes performing a first plasma enhanced chemical vapor deposition (PECVD) process that incudes generating a plasma at a temperature ranging from 220° C. to 400° C., applying a first radio frequency (RF) power ranging from 100 Watts to 1500 Watts, applying a first noble gas flow, applying a first flow rate of silane, and applying a first flow rate of N₂O during a first period of time where the first flow rate of N₂O is at least equal to but not 5 times greater than the first flow rate silane, and wherein forming the second SiON encapsulation layer includes performing a second PECVD process that incudes generating a plasma at a temperature ranging from 220° C. to 400° C., applying a second RF power ranging from 100 Watts to 1500 Watts, applying a second noble gas flow, applying a second flow rate of silane, and applying a second flow rate of N₂O during a second period of time, wherein the second flow rate of N₂O is at least 5 times greater but less than 15 times greater than the second flow rate of silane, and
 20. The method of claim 19, wherein after performing the second PEVCD process, performing a third PEVCD process on the first and second SiON encapsulation, the third PEVCD process including generating a plasma at a temperature ranging from 220° C. to 400° C., applying the second RF power ranging from 100 Watts to 1500 Watts, applying the second noble gas flow, applying the second flow rate of N₂O during a third period of time, wherein the flow rate of silane is terminated during the third PECD process. 